Bistable latches, such as flip-flops, are capable of assuming either of two stable binary output states. The state of the output depends on the states of a data input and a clock signal. Latching flip-flops used in asynchronous systems, wherein a clock signal and a data input signal are switched asynchronously, are typically subject to a third, or metastable, output state. A metastable output may occur if the data input signal is undergoing a transition in its logic state simultaneously with an active edge of the clock signal. In such a case, the output of the flip-flop may latch at an unstable or metastable state somewhere between a logical high state and a logical low state. Such an invalid logic level cannot be interpreted by subsequent logic stages receiving the output signal from the flip-flop, resulting in system errors.
Typically, the metastable state will resolve itself over time as noise in the system stabilizes the output of the flip-flop by driving the output to either a high or low logical state. If noise does not resolve the metastability problem, however, the output of the flip-flop may be hung in an uncertain logical state until the next active clock cycle occurs. Often, the delay associated with either waiting for the output of the flip-flop to stabilize itself or waiting for the next active clock cycle is sufficiently long to cause subsequent logic circuitry to fail.
A known manner of correcting the metastability problem of flip-flops in asynchronous systems is to arrange two separate flip-flops in a cascaded configuration. U.S. Pat. No. 4,929,850 to Breuninger, for example, discloses two D-type flip-flops which are separately driven by clock pulses which are separated in time by a sufficient duration to nearly negate the possibility of the first latch being in its metastable state when the second latch is clocked. The output of the first flip-flop is permitted to stabilize before data is clocked into the second flip-flop.
U.S. Pat. No. 4,800,296 to Ovens, et al. discloses a metastable resistant flip-flop circuit including a single emitter transistor and a dual emitter transistor. During a metastable condition, each of the transistors conducts current. The second emitter on the dual emitter transistor, however, conducts additional current after a delay provided by a second clock, thereby upsetting the metastable condition of the circuit by drawing sufficient additional current to turn the single emitter transistor off.
Optimal design of flip-flop circuits requires minimal circuitry and minimum of additionally introduced delays for the purpose of eliminating metastability problems. Accordingly, it is an object of the present invention to provide a single flip-flop with improved metastability characteristics, comprising standard electrical components, and having no additional timing delays introduced therein by delayed clocking signals.